Xillinx VHDL code error -

i trying write vhdl code gives me more trying write code sequential 5 states ( s0 , s1 , s2 , s3 , s4)

library ieee; use ieee.std_logic_1164.all;  entity seqq port ( seq , clk , reset : in std_logic;        output : out std_logic;          leds : out std_logic_vector( 2 downto 0) ); end seqq;   architecture behavioral of seqq type states ( s0 , s1 , s2 , s3 , s4); signal nxt , prst : states ; begin fb:process(reset, clk) begin if rising_edge(clk)  if reset = '1' prst <='0';  else prst <= nxt ; end if ; end if ; end process fb;comb:process( prst)  begin  case prst  when s0 => if seq = '0' nxt <= s0; elsif seq = '1' nxt <= s1; end if ; leds <= "000"; output <= '0';  when s1 => if seq = '0' nxt <= s2; elsif seq = '1' nxt <= s1; end if ; leds <= "001"; output <= '0';  when s2 => if seq = '0' nxt <= s2; elsif seq = '1' nxt <= s1; end if ; leds <= "010"; output <= '0';  when s3 => if seq = '0' nxt <= s0; elsif seq = '1' nxt <= s4; end if ; leds <= "011"; output <= '0';  when s4 => if seq = '0' nxt <= s0; output <= '1'; elsif seq = '1' nxt <= s1; end if ; leds <= "100"; output <= '0'; end case ; end process comb;   end behavioral; 

and error is

type of prst incompatible type of '0'. 

what can do?

in line

if reset = '1' prst <='0'; 

you assigning '0' prst. if @ error message prst incompatible type of '0', see types don't match.

investigating type of prst, see of type states, enum ranging s0 s4. '0' of type std_logic or bit, not convertible state.

so, propably want (if still ok logic) change assignment of prst s0 instead:

if reset = '1' prst <= s0;