build - Writing makefile to compile several binaries -
i trying write makefile compile 87 files following names: file1.c, file2.c file3.c .... file87.c
i trying compile them separate binaries names: file1, file2, file3 .... file87
in makefile need define following variables each , every 1 of them. this had originally.
file1 = file1 $(file1)_src := \ mydir/file1.c \ mydir/another.c $(file1)_cflags := `pkg-config --cflags glib-2.0` $(file1)_ldflags := -l. `pkg-config --libs glib-2.0` file2 = file2 $(file2)_src := \ mydir/file2.c \ mydir/another.c $(file2)_cflags := `pkg-config --cflags glib-2.0` $(file2)_ldflags := -l. `pkg-config --libs glib-2.0`
also @ end of makefile need store names of binaries
binaries = $(file1) $(file2) ...... $(file87)
i explored loops , define directive in make cannot understand how can neatly in non-cumbersome manner. please note cflags , ldflags same of them.
any inputs or alternative approaches writing makefile welcome.
i wrote based on seldon's answer below, gives error:
srcs = $(wildcard mydir/*.c) tgts = $(srcs:%.c=%) cflags = $$(pkg-config --cflags glib-2.0) ldflags = -l. ldlibs = $$(pkg-config --libs glib-2.0) all: $(tgts) @echo $(srcs) @echo $(tgts) $(tgts) : % : %.o another.o #clean: # rm -f $(tgts) *.o #.phony: clean $ make cc $(pkg-config --cflags glib-2.0) -c -o mydir/another.o mydir/another.c make: *** no rule make target `another.o', needed `mydir/another'. stop.
source:
another.c
# include <stdio.h> # include <stdlib.h> void print_string(const char * file_name, int lineno, const char * func_name) { printf("%s %d %s\n", file_name, lineno, func_name); }
file01.c
int main() { print_string(__file__, __line__, __func__); }
any appreciated.
if variables same programs, use static pattern rule this:
srcs = $(wildcard file*.c) tgts = $(srcs:%.c=%) cflags = $$(pkg-config --cflags glib-2.0) ldflags = -l. ldlibs = $$(pkg-config --libs glib-2.0) all: $(tgts) $(tgts) : % : %.o another.o clean: rm -f $(tgts) *.o .phony: clean
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