vhdl - Instantiating 4 bit Full Adder -

i'm having difficulty instantiating fa0 portion of code. i'm new vhdl maybe more answer help.

this logic 4 module structural code component alu i'm working on.

thank

----------------------------------------------------------------- -- 4-bit adder/subtractor module ----------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all;  entity addsub4     port (addl_subh : in std_logic;         x, y      : in std_logic_vector(3 downto 0);         s         : out std_logic_vector(3 downto 0);         cout, ovf : out std_logic); end addsub4;  architecture addsub4_arch of addsub4      component fa         port (cin, x, y : in std_logic;             s, cout   : out std_logic);     end component fa;      -- let yhat denote signal after y xor addl_subh     signal yhat: std_logic_vector(3 downto 0);      -- let carryout denote cout signal each fa module     signal carryout: std_logic_vector(3 downto 0);   begin      yhat(0) <= y(0) xor addl_subh;     yhat(1) <= y(1) xor addl_subh;     yhat(2) <= y(2) xor addl_subh;     yhat(3) <= y(3) xor addl_subh;      fa0: fa         port map ( cin => addl_subh, x => x(0), y => yhat(0),                 s => s(0), cout => carryout(0));      fa1: fa         port map ( cin => carryout(0), x => x(1), y => yhat(1),                  s => s(1), cout => carryout(1));      fa2: fa         port map ( cin => carryout(1), x => x(2), y => yhat(2),                  s => s(2), cout => carryout(2));      fa3: fa         port map ( cin => carryout(2), x => x(3), y => yhat(3),                  s => s(3), cout => carryout(3));      cout <= carryout(3);     ovf <= carryout(2) xor carryout(3);  end addsub4_arch; 

your code has no errors , should add seperate file project contains fa (full adder) code. example :

library ieee; use ieee.std_logic_1164.all;  entity fa port(x,y,cin : in std_logic;      s,cout  : out std_logic); end entity;  architecture dataflow of fa begin     s <= x xor y xor cin;     cout <= ((x xor y) , cin) or (x , y); end dataflow;