design - VHDL Program counter using signals and previously made components? -

i in middle of project attempting design single cycle cpu. doing without pipe-lining, since add complexity of design. taking baby steps learn this. find myself stuck @ portion attempting code program counter(pc) using made components.

the model of design looks picture here. sorry, no idea why came out dark, if click on it shows correctly. pc , themux both 32 bit components, assume adder well.

here code have been given, implementation begins @ begin statement on line 41. pay no attention now, bunch of random gibberish attempting.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------------------------- entity pc_update     port( clk: in std_logic; -- clock         inch_ldl: in std_logic; -- increment pc = pc + 4 when high,                                 -- load pcinput when low     pcinput: in std_logic_vector(31 downto 0); -- external input pc     instraddr: out std_logic_vector(31 downto 0) ); -- instruction address end entity pc_update; ---------------------------------------------------- architecture pc_update_arch of pc_update     component register32         port( clr: in std_logic; -- async. clear               clk: in std_logic; -- clock                ld: in std_logic; -- load                   d: in std_logic_vector(31 downto 0); -- data input                 q: out std_logic_vector(31 downto 0) ); -- data output     end component register32;      component mux2to1_32         port( sel: in std_logic; -- selection bit input                x0: in std_logic_vector(31 downto 0); -- first input                 x1: in std_logic_vector(31 downto 0); -- second input                  y: out std_logic_vector(31 downto 0)); -- output     end component mux2to1_32;      signal pc_current: std_logic_vector(31 downto 0); -- current state of pc reg             signal pc_add_4: std_logic_vector(31 downto 0); -- output adder      signal pc_next: std_logic_vector(31 downto 0); -- output mux      begin      pc: register32 port map(         clk, q, clr, d);         mux: mux2to1_32 port map(         x0,sel,x1,y);      process (inch_ldl)         begin         wait until (clk = '1');         if  inch_1dl = '0'             instraddr <= x0;         else instraddr <= x1;         end if;     end process;  end architecture pc_update_arch; 

i new have faint idea of how signals work, , no idea how supposed implement components design. confused wasnt asked build adder ahead of time. necessary use component im guessing?

anyhow, have attempted different things stumbled upon searching, such port mapping see. sort of error, error im receiving objects q, clr, , d used not declared. how declare them? if rid of statements, error repeats objects x0, x1, , y. in right direction appreciated. guys!

also, in case need them, register

library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  ---------------------------------------------------  entity register32 port(  clr: in std_logic; -- async. clear clk: in std_logic; -- clock ld: in std_logic; -- load d: in std_logic_vector(31 downto 0); -- data input q: out std_logic_vector(31 downto 0) ); -- data output end entity register32;  ----------------------------------------------------  architecture register32_arch of register32  begin      process(clk, clr)     begin         if clr = '1'             q <= x"00000000";         elsif rising_edge(clk)            if ld = '1'                q <= d;            end if;         end if;     end process; end register32_arch; 

and mux

library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  ---------------------------------------------------  entity mux2to1_32 port( sel: in std_logic; -- selection bit input x0: in std_logic_vector(31 downto 0); -- first input x1: in std_logic_vector(31 downto 0); -- second input y: out std_logic_vector(31 downto 0)); -- output  end entity mux2to1_32;  ----------------------------------------------------  architecture mux2to1_32_arch of mux2to1_32 begin      y <= x1 when (sel = '1') else x0;  end architecture mux2to1_32_arch;  

edit ok, no idea if did correctly, rewrote portmaps. having errors of port names (sel, clk, x0, x1..etc) being "used not initialized. why clr, clk , ld have initial values. once again, no idea if correct, made errors go away. realized never added register32 , mux2to1_32 vhdl files project, , after doing got rid of other errors having.

so stands, code compiles, have included in project vwf simulation file testing, know results gonna incorrect.

i dont know wrong yet, know need pc_add_4. value needs (pc_current + 4), im not sure how this.

here updated portion of code(everything else same)

pc: register32 port map(     clr => '0',      clk => '0',      ld => '1',         q => pc_current,        d => pc_next        );  mux: mux2to1_32 port map(     sel => inch_ldl,      x0 => pcinput ,     x1 => pc_add_4,     y =>  pc_next      );  process (inch_ldl)     begin     if (rising_edge(clk))         if  inch_ldl = '0'             instraddr <= pc_current;         else instraddr <= pc_add_4;         end if;     end if; end process; 

and, in case help, list of errors..im guessing pin related errors because dont have hardware assignments made yet.

1. warning (10541): vhdl signal declaration warning @ pc_update.vhd(38): used implicit default value signal "pc_add_4" because signal never assigned value or explicit default value. use of implicit default value may introduce unintended design optimizations.

2. warning (10492): vhdl process statement warning @ pc_update.vhd(61): signal "clk" read inside process statement isn't in process statement's sensitivity list

3. warning: output pins stuck @ vcc or gnd

4. warning: design contains 34 input pin(s) not drive logic

5. warning: found 32 output pins without output pin load capacitance assignment

6. warning: reserve unused pins setting has not been specified, , default 'as output driving ground'.

7. warning: can't generate programming files because using quartus ii software in evaluation mode

8. warning: no paths found timing analysis

9. critical warning: no exact pin location assignment(s) 66 pins of 66 total pins

second edit yeah fixed code adding pc_add_4 <= (pc_current + 4 ); after port mappings, , adding "clk" process sensitivity list. waveforms in simulation still wrong believe, shown here.

it appears treating inch_ldl clear signal, rather passing pcinput instraddr. due setting of default '0' in port map. did earlier because giving me "used not declared" errors. ill try messing , post findings.

third edit

i have edited code such:

process (inch_ldl, clk)     begin     if rising_edge(clk)         if  (inch_ldl = '0')             instraddr <= pcinput ;         else instraddr <= pc_add_4;         end if;     end if; end process; 

my simulation shows when inch_ldl = 0, pcinput loaded instraddr, however, when inch_ldl = 1, loads value '4', , doesnt increment @ start of every clock cycle supposed to...i need make use of pc_current, not sure how....sicne cant assign 1 signal "pc_current <= pcinput". try more things,in mean time, pointers appreciated.

fourth edit still reading this, , bearing through reading.

i have attempted use pc_next , pc_current in implementation, have run "multiple constant drivers net "pc_next" errors.

my process code:

process (inch_ldl, clk, pc_next, pc_current)     begin     if rising_edge(clk)         if  (inch_ldl = '0')             pc_next <= pcinput;         else pc_next  <= pc_add_4;         end if;     end if;      instraddr <= pc_current;     end process; 

i aware error comes when these assignments made within loops? @ loss here @ try next.

your port maps in first code need ported signals. placing port names of components in port map, incorrect. create signals can connect components, , place them in port map fields instead (to match connections in image).